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IR3092
DATA SHEET
2 PHASE OPTERON, ATHLON, OR VR10.X CONTROL IC
DESCRIPTION
The IR3092 Control IC provides a full featured, single chip solution to implement robust power conversion solutions for three different microprocessor families; 1) AMD Opteron, 2) AMD Athlon or 3) Intel VR10.X family of processors. The user can select the appropriate VID range with a single pin. PWM Control and 2 phase gate drive functions are integrated into a single IC. In addition to CPU power, the IR3092 offers a compact, efficient solution for high current POL converters.
FEATURES
x x x x x x x x x x x x x x x 5 bit or 6 bit VID with 0.5% overall system accuracy Selectable VID Code for AMD Opteron, AMD Athlon or Intel VR10.X Programmable Slew Rate response to "On-the-Fly" VID Code Changes 3.5A Gate Drive Capability Programmable 100KHz to 540KHz oscillator Programmable Voltage Positioning (can be disabled) Programmable Softstart Programmable Hiccup Over-Current Protection with Delay to prevent false triggering Simplified Powergood provides indication of proper operation and avoids false triggering Operates up to 21V input with 7.8V Under-Voltage Lockout 5V UVL with 4.3V Under-Voltage Lockout threshold Adjustable Voltage, 150mA Bias Regulator provides MOSFET Drive Voltage Enable Input OVP Output Available in a 48L MLPQ package
ORDERING INFORMATION
DEVICE IR3092MTR x *IR3092M Samples Only ORDER QUANTITY 3000 per Reel 100 piece strips
PACKAGE INFORMATION
Page 1 of 37
LGND SETBIAS VCC NC NC BIASOUT PWRGD CSINP2 NC VID_SEL NC NC
VID3 VID4 ROSC VOSNSOCSET VDAC VDRP FB EAOUT SS/DEL SCOMP NC
VID2 VID1 VID0 VID5 NC NC ENABLE OVP CSINP1 CSINM NC VCCH1 GAT EH1 PGND1 GAT EL1 VCCL 5VUVL GAT EL2 PGND2 GAT EH2 VCCH2 NC NC NC
IR3092
48LD MLPQ
48L MLPQ (7 x 7 mm Body) o - JA = 27 C/W
06/25/04
IR3092
PIN DESCRIPTION
PIN# PIN SYMBOL PIN DESCRIPTION
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16-17 18 19 20 21 22 23-27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43-44 45 46 47 48 VID3 VID4 ROSC VOSNSOCSET VDAC VDRP FB EAOUT SS/DEL SCOMP N/C LGND SETBIAS VCC N/C BIASOUT PWRGD CSINP2 N/C VID_SEL N/C VCCH2 GATEH2 PGND2 GATEL2 5VUVL VCCL GATEL1 PGND1 GATEH1 VCCH1 NC CSINM1 CSINP1 OVP ENABLE N/C VID5 VID0 VID1 VID2 Inputs to VID D to A Converter Inputs to VID D to A Converter Connect a resistor to VOSNS- to program oscillator frequency and FB, OCSET, BBFB, and VDAC bias currents Remote Sense Input. Connect to ground at the Load. Programs the hiccup over-current threshold through an external resistor tied to VDAC and an internal current source. Regulated voltage programmed by the VID inputs. Current Sensing and Over Current Protection are referenced to this pin. Connect an external RC network to VOSNS- to program Dynamic VID slew rate. Buffered IIN signal. Connect an external RC network to FB to program converter output impedance Inverting input to the Error Amplifier. Converter output voltage is offset from the VDAC voltage through an external resistor connected to the converter output voltage at the load and an internal current source. Bias current is a function of ROSC. Also OVPsense. Output of the Error Amplifier Controls Converter Softstart, Power Good, and Over-Current Timing. Connect an external capacitor to LGND to program the timing. Compensation for the Current Share control loop. Connect a capacitor to ground to set the control loop's bandwidth. Phase 2 is forced to match phase 1's current. No Connect. Local Ground and IC substrate connection External resistor to ground sets voltage at BIASOUT pin. Bias current is a function of ROSC. Power for internal circuitry and source for BIASOUT regulator No Connect. 150mA open-looped regulated voltage set by SETBIAS for GATE drive bias. Open Collector output that drives low during Softstart or any fault condition. Connect external pull-up. Non-inverting input to the Phase 2 Current Sense Amplifier. No Connect. Ground Selects VR10 VID, Float Selects OPTERON VID, VCC Selects ATHLON VID No Connect. Power for Phase 2 High-Side Gate Driver Phase 2 High-Side Gate Driver Output and input to GATEL2 non-overlap comparator. Return for Phase 2 Gate Drivers Phase 2 Low-Side Gate Driver Output and input to GATEH2 non-overlap comparator. Can be used to monitor the driver supply voltage or 5V supply voltage when converting from 5V. An under voltage condition initiates Soft Start. Power for Phase 1 and 2 Low-Side Gate Drivers. Phase 1 Low-Side Gate Driver Output and input to GATEH1 non-overlap comparator. Return for Phase 1 Gate Drivers Phase 1 High-Side Gate Driver Output and input to GATEL1 non-overlap comparator. Power for Phase 1 High-Side Gate Driver Not connected Inverting input to the Phase 1Current Sense Amplifier. Non-inverting input to the Current Sense Amplifier. Output that drives high during an Over-Voltage condition. Enable Input. A logic low applied to this pin puts the IC into Fault mode. No Connect. Inputs to VID D to A Converter Inputs to VID D to A Converter Inputs to VID D to A Converter Inputs to VID D to A Converter
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IR3092
ABSOLUTE MAXIMUM RATINGS
Operating Junction Temperature.................150 C o o Storage Temperature Range......................-65 C to 150 C
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 NAME VID3 VID4 ROSC VOSNSOCSET VDAC VDRP FB EAOUT SS/DEL SCOMP N/C LGND SETBIAS VCC N/C N/C BIASOUT PWRGD CSINP2 N/C VID_SEL N/C N/C N/C N/C N/C VCCH2 GATEH2 PGND2 GATEL2 5VUVL VCCL GATEL1 PGND1 GATEH1 VCCH1 N/C CSINM1 CSINP1 OVP ENABLE N/C N/C VID5 VID0 VID1 VID2 VMAX 30V 30V 30V 0.5V 30V 30V 30V 30V 10V 30V 30V n/a n/a 30V 30V n/a n/a 30V 30V 30V n/a 30V n/a n/a n/a n/a n/a 30V 30V 0.3V 30V 30V 30V 30V 0.3V 30V 30V n/a 30V 30V 30V 30V n/a n/a 30V 30V 30V 30V VMIN -0.3V -0.3V -0.5V -0.5V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V n/a n/a -0.3V -0.3V n/a n/a -0.3V -0.3V -0.3V n/a -0.3V n/a n/a n/a n/a n/a -0.3V -0.3V DC, -2V for 100ns -0.3V -0.3V DC, -2V for 100ns -0.3V -0.3V -0.3V DC, -2V for 100ns -0.3V -0.3V DC, -2V for 100ns -0.3V n/a -0.3V -0.3V -0.3V -0.3V n/a n/a -0.3V -0.3V -0.3V -0.3V ISOURCE 1mA 1mA 1mA 10mA 1mA 1mA 5mA 1mA 10mA 1mA 5mA n/a 50mA 1mA 1mA n/a n/a 250mA 1mA 250mA n/a 1mA n/a n/a n/a n/a n/a n/a 3A for 100ns, 200mA DC 3A for 100ns, 200mA DC 3A for 100ns, 200mA DC 1mA n/a 3A for 100ns, 200mA DC 3A for 100ns, 200mA DC 3A for 100ns, 200mA DC n/a n/a 250mA 250mA 1mA 1mA n/a n/a 1mA 1mA 1mA 1mA ISINK 1mA 1mA 1mA 10mA 1mA 1mA 5mA 1mA 20mA 1mA 5mA n/a 1mA 1mA 250mA n/a n/a 1mA 20mA 1mA n/a 1mA n/a n/a n/a n/a n/a 3A for 100ns, 200mA DC 3A for 100ns, 200mA DC n/a 3A for 100ns, 200mA DC 1mA 3A for 100ns, 200mA DC 3A for 100ns, 200mA DC n/a 3A for 100ns, 200mA DC 3A for 100ns, 200mA DC n/a 1mA 1mA 1mA 1mA n/a n/a 1mA 1mA 1mA 1mA
o
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IR3092
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over: 7.3V VCC 21V, 4V VCCL 14V, o o 4V VCCHX 28V, CGATEHX =3.3nF, CGATELX =6.8nF, 0 C TJ 125 C PARAMETER VDAC Reference System Set-Point Accuracy TEST CONDITION -0.3V 92616- 9 &RQQHFW )% WR EAOUT, Measure V(EAOUT) - V(VOSNS-) deviation from Table 1. Applies to all VID codes. RROSC = 42k 9'$& 2&6(7 RROSC = 42k 9'$& 2&6(7 VID_SEL=0, Referenced to VOSNSVID_SEL=Float, Referenced to VOSNSMIN TYP 0.5 MAX UNIT %
Source Current Sink Current VID Input Threshold, INTEL VID Input Threshold, AMD VID_SEL OPTERON Threshold VID_SEL ATHLON Threshold VID_SEL Float Voltage VID_SEL Pull-up Resistance VID_SEL Pull-down Resistance VID Pull-up Current VID Float Voltage VID = 11111 Fault Blanking Error Amplifier Input Offset Voltage
56 50 0.4 1.3 1.0 3.0 2.1 30 60 9 4.5 0.5 -5
62 58 0.6 1.5 1.2 3.4 2.6 60 190 15 4.9 1.7 -1
71 67 0.8 1.7 1.4 3.8 3.2 100 375 27 5.2 4.1 3
PA PA V V V V V k k PA V Ps mV
Tracks ATHLON threshold V(VID_SEL)<2.1V V(VID_SEL)>3.2V VID0-5 = 1V Referenced to LGND Delay to PWRGD assertion Connect FB to EAOUT, Measure V(EAOUT)-V(VDAC). From Table 1. Applies to all VID codes and -0.3V VOSNS- 9 1RWH RROSC = 42k Note 1 Note 1 Note 1, 50mV FB signal
FB Bias Current DC Gain Gain-Bandwidth Product Slew Rate Source Current Sink Current Max Voltage Min Voltage VDRP Buffer Amplifier Positioning Offset Voltage Output Voltage Range Source Current Sink Current
28 90 4 280 .75 4.5
30.5 100 7 1.25 380 1.0 4.9 90 0
33 105
PA dB MHz V/Ps PA mA V mV mV V mA PA
500 1.5 5.3 150 125 3.75 20 400
V(VDRP) - V(VDAC) with CSINMX=CSINPX=0, Note 1.
-125 0.2 5 200
10 280
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IR3092
PARAMETER Oscillator Switching Frequency Phase1 to Phase2 Shift BIASOUT Regulator SETBIAS Bias Current Set Point Accuracy BIASOUT Dropout Voltage BIASOUT Current Limit Soft Start and Delay SS/DEL to FB Input Offset Voltage Charge Current Hiccup Discharge Current OC Discharge Current Charge/Discharge Current Ratio Charge Voltage Delay Comparator Threshold Delay Comparator Hysteresis Discharge Comparator Threshold Over-Current Comparator Input Offset Voltage OCSET Bias Current Max OCSET Set Point Under-Voltage Lockout VCC Start Threshold VCC Stop Threshold VCC Hysteresis 5VUVL Start Threshold 5VUVL Stop Threshold 5VUVL Hysteresis 5VUVL Input Resistance PWRGD Output Output Voltage Leakage Current Enable Input Threshold, INTEL Threshold, AMD Input Resistance Pull-up Voltage TEST CONDITION RROSC = 42k GATEH1 rise to GATEH2 rise RROSC = 42k V(SETBIAS)-V(BIASOUT) @ 100mA I(BIASOUT)=100mA,Threshold when V(SETBIAS)-V(BIASOUT)=0.45V MIN 160 155 105 0.1 1.2 150 With FB = 0V, adjust V(SS/DEL) until EAOUT drives high 0.8 25 2.5 25 9 3.8 200 15 200 TYP 200 170 115 0.3 1.8 300 1.3 55 5.5 45 10 4.0 240 30 260 MAX 240 190 125 0.55 2.5 450 1.8 75 7.5 70 11 4.2 280 45 350 UNIT kHz PA V V mA V PA PA PA PA/PA V mV mV mV
Relative to Charge Voltage
V(OCSET)-V(VDAC), CSIN=CSINP1=CSINP2, Note 1. RROSC = 42k
-125 28 3.95 7.2 6.7 450 4.05 3.92 100 24
0 30
125 33
mV PA V V V mV V V mV k mV PA V V k V
Start - Stop
Start - Stop To LGND I(PWRGD) = 4mA V(PWRGD) = 5.5V VID_SEL=0, Referenced to VOSNSVID_SEL=Float, Referenced to VOSNS-
7.8 7.3 500 4.3 4.125 175 36 150 0
8.3 7.8 750 4.55 4.33 250 72 300 10 0.8 1.7 20 3.7
0.4 1.3 7.5 2.4
0.6 1.5 15 3.0
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IR3092
PARAMETER Gate Drivers GATEH Rise Time GATEH Fall Time GATEL Rise Time GATEL Fall Time High Voltage (AC) Low Voltage (AC) GATEL low to GATEH high delay GATEH low to GATEL high delay Disable Pull-Down Current PWM Comparator Propagation Delay Common Mode Input Range Internal Ramp Start Voltage Internal Ramp Amplitude Current Sense Amplifier CSINP1&2 Bias Current CSINM Bias Current Input Current Offset Ratio Average Input Offset Voltage Offset Voltage Mismatch o Gain at TJ = 25 C o Gain at TJ = 125 C Gain Mismatch Differential Input Range Common Mode Input Range TEST CONDITION VCCHX = 12V, Measure 2V to 9V transition time, Note 1 VCCHX = 12V, Measure 9V to 2V transition time, Note 1 VCCL = 12V, Measure 2V to 9V transition time, Note 1 VCCL = 12V, Measure 9V to 2V transition time, Note 1 Measure VCCL - GATELX or VCCHX - GATEHX, Note 1 Measure GATELX or GATEHX, Note 1 VCCHX = VCCL = 12V, Measure the time from GATELX falling to 2V to GATEHX rising to 2V, Note 1 VCCHX = VCCL = 12V, Measure the time from GATEHX falling to 2V to GATELX rising to 2V, Note 1 GATHX or GATELX=2V with VCC = 0V. Measure Gate pull-down current VCCHX = VCCL = 12V, Measure the time from EAOUT fall crossing VDAC to GATEHX falling to 11V. (Note 1) 0.45 40 -0.5 -1 0.7 -4 -8 22.0 18.5 -0.3 -25 0 MIN TYP 11 11 20 20 0 0 35 35 35 MAX 40 40 65 65 0.5V 0.5V 60 60 50 UNIT ns ns ns ns V V ns ns PA ns V
V mV / %DTC
20 20 20
100
150 4 0.9 75 0.1 0.2 2.6 4 8 25.0 24.0 0.3 75 2.8
0.7 57 -0.2 -0.4 1.7 0 0 23.5 20.0 0
CSINM/CSINPX (VDRP-VDAC)/GAIN withCSINX=0, Note1. Monitor I(SCOMP)
PA PA PA/PA mV mV V/V V/V V/V mV V
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IR3092
PARAMETER Share Adjust Error Amplifier Input Offset Voltage MAX Duty Cycle Adjust Ratio MIN Duty Cycle Adjust Ratio Transconductance SCOMP Source/Sink Current Equal Duty Cycle Comparator Threshold Duty Cycle Match at Startup SCOMP Precharge Current 0% Duty Cycle Comparator Threshold Voltage Propagation Delay Body Braking Disable Comparator Threshold OVP VR10 Comparator Threshold AMD Comparator Threshold Propagation Delay Source Current Pull Down Resistance High Voltage General VCC Supply Current VOSNS- Current VCCHX Supply Current (12V) VCCHX Supply Current (28V) VCCL Supply Current TEST CONDITION Note 1 Duty Cycle of GATEH2 to GATEH1 Duty Cycle of GATEH2 to GATEH1 Note 1 MIN -5 1.5 0.6 100 15 0.45 -5 250 100 TYP 0 2 0.5 200 28 0.7 0 420 150 200 50 80 MAX 5 3 0.4 300 40 0.85 5 600 200 320 110 UNIT mV %/% %/% PA/V PA V % PA mV ns mV
DTC GATEH1 - DTC GATEH2 V(SS/DEL)=0 (Internal Ramp1 Start Voltage) - (0DC Threshold) VCCL = 12V. Step EAOUT from .8V to .3V and measure time to GATELX transition to < 11V. Compare V(FB) to V(VDAC)
VID_SEL=0V. Compare to V(VDAC) Float VID_SEL. Compare to V(VDAC) VCCL = 12V. V(EAOUT)=0V. Step FB 460mV above V(VDAC). Measure time to GATELX transition to >1V. OVP to PGND1 I(OVP)=10mA, V(VCC)-V(OVP) -0.3V VOSNS- 0.3V, All VID Codes
120 360
145 480 200 20 45 1.2 29 3 5 7 10
180 600 300
mV mV ns mA k V mA mA mA mA mA
10 20 .8 23 2 3 5 5
80 1.6 34 4 7 9 16
Note 1: Guaranteed by design, but not tested in production Note 2: VDAC Output is trimmed to compensate for Error Amp input offsets errors
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IR3092
TYPICAL OPERATING CHARACTERISTICS
I(FB) and I(OCSET) Currents vs. ROSC
90 80 70 60
180 160 140 120 uA 100 80 60 40 20 0
I(VDAC) Sink and Source Currents vs. ROSC I(VDAC) Source Current I(VDAC) Sink Current
I(FB) in uA I(OCSET) in uA
uA
50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100
10
20
30
40
ROSC in Kohms
50 60 70 ROSC in Kohms
80
90
100
550 500 450 400 350 300 250 200 150 100 50 0 10 20
Oscillator Frequency vs. ROSC
300 250 200 uA 150 100 50 0
I(SETBIAS) vs. ROSC
Frequency in KHz
30
40
50 60 70 ROSC in Kohms
80
90
100
10
20
30
40
50
60
70
80
90
100
ROSC in Kohms
Frequency and Bias Current Accuracy vs. ROSC (includes temperature)
6 5 +/-3 Sigma Variation (%)
Peak Gate Drive Current vs. Load Capacitance
4.0
3.5
I(GATEX) in Amps
4
3.0
I(RISE) I(FALL)
Frequency
3 2 1 0 10 20 30 40 50 60 70 80 90 100 ROSC (KOhm)
FB Bias OCSET Bias SETBIAS
2.5
c
2.0
1.5
1.0 1 3.5 6 8.5 11 13.5 16 18.5 21
C(GATEX) in nF
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IR3092
TYPICAL OPERATING CHARACTERISTICS
Error Amplifier Frequency Response
100
0
-100
93dB DC gain 88 Phase Margin 3.1MHz Crossover
-180 1.0Hz 10Hz 100Hz DB(V(comp)) P(V(comp))
1.0KHz
10KHz Frequency
100KHz
1.0MHz
10MHz 100MHz
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IR3092
IR3092 THEORY OF OPERATION
IOVP VCC ON LGND
-
OVP
ROSC FB IROSC EAOUT IN
CLK1
VCCH1
UVL
PGND DRIVE
45k
IROSC
IROSC
GATEHI OL_OUT
RESET DOMINANT S Q QB OL_IN GateHI
GATEHI1
SETBIAS
4 X IROSC
+
1.243 Oscillator
CLK2
BIASOUT
7.8V START 7.3V STOP OVP Comparator UVL
+
R RSFF
BB DISABLE COMPARATOR PGND DRIVE
+
FB
IROSC/2
+
VCCL OL_IN OL_OUT GATELO
PWRGD
4.300V START 4.125V STOP
AMD=450mV INTEL=150mV
80mV
PWM COMPARATOR
VDAC 0% DUTY CYCLE
+
OVER CURRENT OCSET
+
0.55V summer
1.3V
IROSC DELAY
+
VDAC
240mV chrg, 210mV dischrg 4V 55U SS ON FAULT LATCH Q S
+
EQUAL DUTY CY CLE COMPARATOR
+
RESET DOMINANT S Q QB
5.5U
45U
0.7V DAC BUFFER RSFF
R
3V
Discharge Comparator R 1.9us BLANKING SET DOMINANT
15k ENABLE
+
0.26V
+
DAC DEFAULTS TO VR10 WITH VID_SEL GROUNDED
F11111 ATHLON_DAC OPTERON_DAC VID0 VID1 VID2 VID3 VID4 DAC OUT VOSNSVID5 FAST DAC
IN
IROSC
PGND DRIVE
IROSC
+
GATEHI OL_OUT
OL_IN GateHI
AMD=1.5V INTEL=0.6V VOSNSVID_SEL 4.9V 5V 3.3V 1
+
PWM COMPARATOR VCCL U18 0 TO IROSC*3/4 10p 0.7V OL_IN IN GateLO PGND DRIVE OL_OUT GATELO
18uA
H FORCES IROSC/2 AT SS<0.7V
3.4V 60K
+
110K
1.2V VID0 VID1 VID2 VID3 VID4 VID5 VOSNSVDAC
Figure 1 - IR3092 Block Diagram
PWM Operation The IR3092 is a fully integrated 2 phase interleaved PWM control IC which uses voltage mode control with trailing edge modulation. A high-gain wide-bandwidth voltage type Error Amplifier in the control IC is used for the voltage control loop. The PWM block diagram of the IR3092 is shown in Figure 2. Refer to Figure 3. Upon receiving a clock pulse, the RSFF is set, the internal PWM ramp voltage begins to increase, the low side driver is turned off, and the high side driver is then turned on. For phase 1, an internal 10pf capacitor is charged by a current source that's proportional to the switching frequency resulting in a ramp rate of 57mV per percent duty cycle. For example, if the steady-state operating switch node duty cycle is 10%, then the internal ramp amplitude is typically 570mV from the starting point (or floor) to the crossing of the EAOUT control voltage. When the PWM ramp voltage exceeds the Error Amplifier's output voltage, the RSFF is reset. This turns off the high side driver, turns on the low side driver, and discharges the PWM ramp to 0.7V until the next clock pulse.
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-
OFF
-
+
-
+ -
+
Sof tStart_Clamp
+
-
DISABLE X25
+
Error_Amp
Share Adjust Error Amp
summer VDRP
+
+
-
-
-
+
-
-
-
5VUVL
+
10p 0.7V
IN GateLO
GATEL1
PGND1 VDAC
X25
CSINP1
-
CSINM
CSINP2
SCOMP
VCCH2
GATEH2
GATEL2
PGND2
IR3092
ROSC U39
IROSC
CLK1 CLK2
RSFF S
+
ROSC
OSCBLOCK
QB R RESET DOMINANT IROSC/2 GATEH1
Q
CLK2
PWM COMPARATOR
VIN
BB DISABLE
-
80mV VDAC CDAC RDAC VOSNSVDAC ERROR AMPLIFIER
+
1 10p 0.7V GATEL1 RCS1
2 CCS1
FB
0.55V IROSC
0% DUTY CY CLE CLK2 PWM COMPARATOR
-
RCOMP EAOUT
+
QB R RESET DOMINANT IROSC
Q
CCOMP
VDRP BUFFER RDRP VDRP
+
Share Adjust Error Amp
+ 0 TO IROSC*3/4
RFB SCOMP
CSC2
RSC2 VDAC X24.5
Figure 2 - PWM Block Diagram
The RSFF is reset dominant allowing both phases to go to zero duty cycle within a few tens of nanoseconds in response to a load step decrease. Phases can overlap and go to 100% duty cycle in response to a load step increase with turn-on gated by the clock pulses. An Error Amplifier output voltage greater than the common mode input range of the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This arrangement guarantees the Error Amplifier is always in control and can demand 0 to 100% duty cycle as required. It also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of most systems. The inductor current will increase much more rapidly than decrease in response to load transients. This control method is designed to provide "single cycle transient response" where the inductor current changes in response to load transients within a single switching cycle maximizing the effectiveness of the power train and minimizing the output capacitor requirements.
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+ -
+
RSFF S GATEH2
VIN VOUT SENSE+ 1 GATEL2 RCS2 CCS2 2 VOUT+ COUT VOUTVOUT SENSE-
10p
0.7V
VDAC X24.5
+
CSINP2
+
CSINM CSINP1
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IR3092
50% INTERNAL OSCILLATOR RAMP DUTY CYCLE
CLK1
CLK2
RAMP2 MIN DUTY CYCLE ADJUST FIXED RAMP1 RAMP2
RAMP2 MAX DUTY CYCLE ADJUST
EAOUT
0.7V RAMP1 SLOPE = 57mV / % DC THE SHARE ADJUST ERROR AMPLIFIER CAN CHANGE THE PULSE WIDTH OF RAMP2 FROM 0.5x RAMP1 TO 2.0x RAMP1 TO FORCE CURRENT SHARING.
Figure 3 - 2 Phase Oscillator and PWM Waveforms Body Braking
TM
In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in response to a load step decrease is; TSLEW = [L x (IMAX - IMIN)] / Vout The slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in response to a load step decrease. The switch node voltage is then forced to decrease until conduction of the synchronous rectifier's body diode occurs. This increases the voltage across the inductor from Vout to Vout + VBODY DIODE. The minimum time required to reduce the current in the inductor in response to a load transient decrease is now; TSLEW = [L x (IMAX - IMIN)] / (Vout + VBODY DIODE) Since the voltage drop in the body diode is often higher than output voltage, the inductor current slew rate can be increased by 2X or more. This patent pending technique is referred to as "body braking" and is accomplished through the "0% Duty Cycle Comparator". If the Error Amplifier's output voltage drops below 0.55V, this comparator turns off the low side gate driver. Figure 4 depicts PWM operating waveforms under various conditions
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IR3092
CLK1 PULSE
EAOUT PWM Ramp1 0.7V 0.6V
GATEH1
GATEL1
STEADY-STATE OPERATION
DUTY CYCLE INCREASE DUE TO LOAD INCREASE
DUTY CYCLE DECREASE DUE TO LOAD DECREASE (BODY BRAKING) OR FAULT
STEADY-STATE OPERATION
Figure 4 - PWM Operating Waveforms Current Sense Amplifier A high speed differential current sense amplifier is shown in Figure 5. Its gain decreases with increasing temperature and is nominally 24.5 at 25C and 20 at 125C (-1400 ppm/C). This reduction of gain tends to compensate the 3850 ppm/C increase in inductor DCR. Since in most designs the IR3092 IC junction is hotter than the inductors these two effects tend to cancel such that no additional temperature compensation of the load line is required. The current sense amplifier can accept positive differential input up to 75mV and negative up to -20mV before clipping. The output of the current sense amplifier is summed with the DAC voltage which is used for over current protection, voltage positioning and current sharing.
vL iL L Rs CSA RL Cs vc Vo Co
CO
Figure 5 - Inductor Current Sensing and Current Sense Amplifier VCC Under Voltage Lockout (UVLO) The VCC UVLO function monitors the IR3092's VCC supply pin and ensures enough voltage is available to power the internal circuitry. During power-up the fault latch is reset when VCC exceeds 7.8V and all other faults are cleared. The fault latch is set when VCC drops below 7.3V, resulting in 500mV of nominal VCC hysteresis for powering up into a load. 5VUVL Under Voltage Lockout (5VUVL) The 5VUVL function is provided for converters using a separate voltage supply other than VCC for gate driver bias. The 5VUVL comparator prevents operation by discharging SS/DEL and forcing EAOUT low. The 5VUVL comparator has an OK threshold of 4.3V ensuring adequate gate drive voltage is present and a fault threshold of 4.125V.
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IR3092
Power Good Output The PWRGD pin is an open-collector output and should be pulled up to a voltage source through a resistor. During soft start, the PWRGD remains low until the output voltage is in regulation and SS/DEL is above 3.75V. The PWRGD pin becomes low if the fault latch is set. A high level at the PWRGD pin indicates that the converter is in operation and has no fault, but does not ensure the output voltage is within the specification. Output voltage regulation within the design limits can logically be assured however, assuming no component failure in the system. Tri-State Gate Drivers The gate drivers can deliver over 3.5A peak current. An adaptive non-overlap circuit monitors the voltage on the GATEHX and GATELX pins to prevent MOSFET shoot-through current while minimizing body diode conduction. The Error Amplifier output of the Control IC drives low in response to any fault condition such as VCC input under voltage or output overload. The 0% duty cycle comparator detects this and drives both gate outputs low. This tri-state operation prevents negative inductor current and negative output voltage during power-down. The Gate Drivers revert to a high impedance "off" state at VCCL and VCCHX supply voltages below the normal operating range. An 80k UHVLVWRU LV FRQQHFWHG DFURVV WKH *$7(; DQG 3*1'; SLQV WR SUHYHQW WKH *$7(; YROWDJH IURP ULVLQJ GXH to leakage or other cause under these conditions. Over Voltage Protection (OVP) The output Over-Voltage Protection comparator monitors the output voltage through the FB pin, the positive remote sense point. If FB exceeds VDAC plus 145mV (for VR10.X, 480mV for OPTERON and ATHLON, selected with the VID_SEL pin), both GATEL pins drive high and the OVP pin sources up to 10mA. The OVP circuit over-rides the normal PWM operation and will fully turn-on the low side MOSFET within approximately 150ns. The low side MOSFET will remain ON until the over-voltage condition ceases. The lower MOSFETs alone can not clamp the output voltage however an SCR or N-MOSFET could be triggered by the OVP pin to prevent processor damage. Error Amplifier compensation can slow down the response to an OVP condition if the voltage loop is too slow, which is usually not the case. The FB pin can only respond to an over-voltage condition once the EAOUT voltage has reached its minimum. Until then, the FB pin is modified by the falling EAOUT voltage so FB is equal to VDAC. The Error Amplifier compensation slew current generates a voltage across the RFB resistor that will mask the output voltage OVP condition. Again, for a typical fast voltage loop compensation scheme, a fairly large resistor is placed in series with the EAOUT to FB compensation capacitor to speed up the loop which results in no noticeable OVP sensing delay. The overall system must be considered when designing for OVP. In many cases the over-current protection of the AC-DC or DC-DC converter supplying the multiphase converter will be triggered thus providing effective protection without damage as long as all PCB traces and components are sized to handle the worst-case maximum current. If this is not possible, a fuse can be added in the input supply to the multiphase converter. One scenario to be careful of is where the input voltage to the multiphase converter may be pulled below the level where the ICs can provide adequate voltage to the low side MOSFET thus defeating OVP. A Body Braking Disable Comparator has been included to prevent false OVP firing during dynamic VID down changes. TM The BB DISABLE Comparator disables Body Braking when FB exceeds VDAC by 80mV. The low side MOSFETs will then be controlled to keep V(FB) and V(VOUT) within 80mV of V(VDAC), below the 150mV INTEL OVP trip point.
TM
Page 14 of 37
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APPLICATIONS INFORMATION
VIN CIN VIN ENABLE OVP CBST1 VID5 VID0 VID1 VID2 VID3 VID4 RROSC 1 RCS1 CCS1 2 VOUT SENSE+ VOUT+
GNDIN
COUT VOUTVID2 VID1 VID0 VID5 NC NC ENABLE OVP CSINP1 CSINM NC VCCH1 VIN VOUT SENSE-
CDAC RFB RDAC RDRP
ROCSET
RCOMP
CCOMP CSC2 CSS RSC2
CsenseVIN CVCC
LGND SETBIAS VCC NC NC BIASOUT PWRGD CSINP2 NC VID_SEL NC NC
VID3 VID4 ROSC VOSNSOCSET VDAC VDRP FB EAOUT SS/DEL SCOMP NC
IR3092
48LD MLPQ
GATEH1 PGND1 GATEL1 VCCL 5VUVL GATEL2 PGND2 GATEH2 VCCH2 NC NC NC
CBST2
1 RCS2
2
CCS2
CBIAS
RSET
POWERGOOD
Figure 6 - System Diagram VID Control The IR3092 provides three different microprocessor solutions. The VID_SEL pin selects the appropriate Digital-to-Analog Converters (DAC), VID threshold voltages, and Over Voltage Protection (OVP) threshold for VR10.X, OPTERON, or ATHLON solutions. AMD VID codes are shown in Table 1; Intel VID codes are found in Table 2. The DAC output voltage is available at the VDAC pin. A detailed block diagram of the VID control circuitry can be found in Figure 7. The VID pins are internally pulled up to 4.9V by 18uA current sources. The VID input comparators have a 0.6V threshold for VR10.X or 1.5V threshold for OPTERON and ATHLON. The selected DAC voltage is provided at the Error Amplifier positive input and to the VDAC pin by the trans-conductance DAC Buffer. The VDAC voltage is trimmed to the Error Amplifier output voltage with EAOUT tied to FB via an accurate resistor. This compensates DAC Buffer input offset, Error Amplifier input offset, and errors in the generation of the FB bias current which is based on RROSC. This trim method provides 0.5% system accuracy. The IR3092 can accept changes in the VID code while operating and vary the VDAC voltage accordingly. The IR3092 detects a VID change and blanks the DAC output response for 400ns to verify the new code is valid and not due to skew or noise. The sink/source capability of the VDAC buffer amp is programmed by the same external resistor that sets the oscillator frequency, RROSC. The slew rate of the voltage at the VDAC pin can be adjusted by an external capacitor between VDAC pin and the VOSNS- pin. A resistor connected in series with this capacitor is required to compensate the VDAC buffer amplifier. Digital VID transitions result in a smooth analog transition of the VDAC voltage and converter output voltage minimizing inrush currents in the input and output capacitors and overshoot of the output voltage. Page 15 of 37 06/25/04
IR3092
18uA 4.9V
VID=11111X FAULT BLANKING, 3.3us DIGITAL TO ANALOG CONVERTER
TO FAULT
VID5 VID0 VID1 VID2 VID3 VID4
VID INPUT COMPARATORS (1 OF 6 SHOWN)
SHOWN DEFAULT TO VR10 WITH VID_SEL GROUNDED
+ -
"SLOW" VDAC DAC BUFFER
VDAC
"FAST" VDAC DAC DEFAULTS TO VR10 WITH VID_SEL GROUNDED HAMMER DAC ATHLON DAC
+
IROSC
0.6V
1.5V
5V 2.6V FLOAT VOLTAGE 3.3V
+
H=HAMMER
60K
110K
1.2V
VID_SEL
3.4V
VOSNS-
VID = 11111X Fault VID codes of 111111 and 111110 will set the fault latch and disable the Error Amplifier. Slew Rate Programming Capacitor CDAC and Resistor RDAC VDAC sink current ISINK and source current ISOURCE are determined by RROSC, and their value can be found using the curve in the Typical Operating Characteristics. The slew rate of VDAC down-slope SRDOWN can be programmed by the external capacitor CDAC as defined in Equation (1) and shown in Figure 6. Resistor RDAC is used to compensate VDAC circuit and is determined by Equation (2). The slew rate of VDAC up-slope SRUP is proportional to the down-slope slew rate SRDOWN and is given by Equation (3).
R DAC
SRUP
C DAC
2
I SOURCE C DAC
Page 16 of 37
+ -
H=ATHLON
Figure 7- VID Control Block Diagram
C DAC
I SINK SRDOWN
(1)
0.5
3.2 10
15
(2) (3)
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IR3092
Table 1A. AMD OPTERON VID VID_SEL Open. V(VDAC) is prepositioned 50mV higher than Vout values listed below for load positioning. Vout is measured at EAOUT with ROSC=42K and a 1690 ohm resistor connecting FB to EAOUT to cancel the 50mV pre-position offset. Vout VID4 VID3 VID2 VID1 VID0 (V) 0 0 0 0 0 1.550 0 0 0 0 1 1.525 0 0 0 1 0 1.500 0 0 0 1 1 1.475 0 0 1 0 0 1.450 0 0 1 0 1 1.425 0 0 1 1 0 1.400 0 0 1 1 1 1.375 0 1 0 0 0 1.350 0 1 0 0 1 1.325 0 1 0 1 0 1.300 0 1 0 1 1 1.275 0 1 1 0 0 1.250 0 1 1 0 1 1.225 0 1 1 1 0 1.200 0 1 1 1 1 1.175 1 0 0 0 0 1.150 1 0 0 0 1 1.125 1 0 0 1 0 1.100 1 0 0 1 1 1.075 1 0 1 0 0 1.050 1 0 1 0 1 1.025 1 0 1 1 0 1.000 1 0 1 1 1 0.975 1 1 0 0 0 0.950 1 1 0 0 1 0.925 1 1 0 1 0 0.900 1 1 0 1 1 0.875 1 1 1 0 0 0.850 1 1 1 0 1 0.825 1 1 1 1 0 0.800 4 1 1 1 1 1 OFF Note: 4 Output disabled (Fault mode) Table 1B. AMD ATHLON VID VIDSEL to VCC. V(VDAC) is prepositioned 50mV higher than Vout values listed below for load positioning. Vout is measured at EAOUT with ROSC=42K and a 1690 ohm resistor connecting FB to EAOUT to cancel the 50mV pre-position offset. Vout VID4 VID3 VID2 VID1 VID0 (V) 0 0 0 0 0 1.850 0 0 0 0 1 1.825 0 0 0 1 0 1.800 0 0 0 1 1 1.775 0 0 1 0 0 1.750 0 0 1 0 1 1.725 0 0 1 1 0 1.700 0 0 1 1 1 1.675 0 1 0 0 0 1.650 0 1 0 0 1 1.625 0 1 0 1 0 1.600 0 1 0 1 1 1.575 0 1 1 0 0 1.550 0 1 1 0 1 1.525 0 1 1 1 0 1.500 0 1 1 1 1 1.475 1 0 0 0 0 1.450 1 0 0 0 1 1.425 1 0 0 1 0 1.400 1 0 0 1 1 1.375 1 0 1 0 0 1.350 1 0 1 0 1 1.325 1 0 1 1 0 1.300 1 0 1 1 1 1.275 1 1 0 0 0 1.250 1 1 0 0 1 1.225 1 1 0 1 0 1.200 1 1 0 1 1 1.175 1 1 1 0 0 1.150 1 1 1 0 1 1.125 1 1 1 1 0 1.100 4 1 1 1 1 1 OFF
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Table 2. Intel VR10.X VID (VID_SEL Grounded, measured at EAOUT=FB. ) Processor Pins (0 = low, 1 = high)
VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID2 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 VID1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 VID0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID5 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Vout (V) 0.8375 0.8500 0.8625 0.8750 0.8875 0.9000 0.9125 0.9250 0.9375 0.9500 0.9625 0.9750 0.9875 1.0000 1.0125 1.0250 1.0375 1.0500 1.0625 1.0750 1.0875 4 OFF 4 OFF 1.1000 1.1125 1.1250 1.1375 1.1500 1.1625 1.1750 1.1875 1.2000
Processor Pins (0 = low, 1 = high)
VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID2 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 VID1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 VID0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID5 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Note: 4. Output disabled (Fault mode)
Vout (V) 1.2125 1.2250 1.2375 1.2500 1.2625 1.2750 1.2875 1.3000 1.3125 1.3250 1.3375 1.3500 1.3625 1.3750 1.3875 1.4000 1.4125 1.4250 1.4375 1.4500 1.4625 1.4750 1.4875 1.5000 1.5125 1.5250 1.5375 1.5500 1.5625 1.5750 1.5875 1.6000
Oscillator Resistor RROSC The oscillator frequency is programmable from 100kHz to 540kHZ with an external resistor RROSC as shown in Figure 6. The oscillator generates an internal 50% duty cycle saw tooth signal (Figure 4.) that is used to generate 180 out-of-phase timing pulses to set Phase 1 and 2 RS flip-flops. Once the switching frequency is chosen, RROSC can be determined from the curve in the I(SETBIAS) vs. Rosc curve in the Typical Operating Characteristics Section. Soft Start, Over-Current Fault Delay, and Hiccup Mode The IR3092 has a programmable soft-start function to limit the surge current during converter power-up. A capacitor connected between the SS/DEL and LGND pins controls soft start timing as well as over-current protection delay and hiccup mode timing. Figure 8 depicts the various operating modes of the SS/DEL function. Under a no fault condition, the SS/DEL capacitor will charge. The SS/DEL charge soft-start duration is controlled by a 55uA charge current which charges CSS up to 4.0V. The Error Amplifier output is clamped low until SS/DEL reaches 1.3V. The Error Amplifier will then regulate the converter's output voltage to match the SS/DEL voltage less the 1.3V offset until it reaches the level determined by the VID inputs. The PWRGD signal is asserted once the SS/DEL voltage exceeds 3.75V.
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VCC and 5VUVL Under Voltage Lock Outs, a VID=11111x fault, or low Enable pin immediately set the fault latch causing SS/DEL to begin discharging. The hiccup duration is controlled by a 5.5uA discharge current until the Discharge Comparator Threshold of 0.26V is reached. If the fault has cleared, the fault latch will reset allowing a normal soft-start to occur. A delay is included if an over-current condition occurs after a successful soft start sequence. This is required since overcurrent conditions can occur as part of normal operation due to load transients or VID transitions. If an over-current fault occurs during normal operation, the Over Current Comparator will initiate the discharge of the capacitor at SS/DEL but will not set the fault latch immediately. If the over-current condition persists long enough for the SS/DEL capacitor to discharge below the 3.75V threshold of the delay comparator, the Fault latch will be set pulling the Error Amplifier's output low, inhibiting switching and de-asserting the PWRGD signal. An additional discharge current is introduced during an over current condition. The 5.5uA discharge current results in a long delay duration where SS/DEL discharges from its 4V peak to the 3.75V fault delay threshold. This potentially long over-current protection activation delay could result in potential power stage damage therefore an additional 45uA discharge current source assists the 5.5uA discharge current if an over current condition is occurring and the SS/DEL capacitor is above 3.75V. 30mV of hysteresis is included in the Delay Comparator to prevent PWRGD chatter when SS/DEL is at the delay threshold. The SS/DEL capacitor will continue to discharge until it reaches 0.26V where the fault latch is reset allowing a normal soft start to occur. If an over-current condition is again encountered during the soft start cycle, the fault latch will be set without any delay and hiccup mode will begin. During hiccup mode the 10 to 1 charge to discharge ratio results in a 9% hiccup mode duty cycle regardless of at what point the over-current condition occurs. The converter can be disabled if the SS/DEL pin is pulled below 0.9V.
VCC (12V) 4.3V 5VUVL 3.75V SS/DEL 1.3V
7.6V UVLO
VOUT
PWRGD
OCP THRESHOLD IOUT START-UP (5VUVL GATES FAULT MODE) NORMAL OPERATION (VOUT CHANGES DUE TO LOAD AND VID CHANGES) OCP DELAY HICCUP OVER-CURRENT PROTECTION RE-START AFTER OCP CLEARS POWER-DOWN (VCC GATES FAULT MODE)
Figure 8 - Operating Waveforms
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Soft-start delay time tSSDEL is the time to charge SS/DEL up to 1.3V. After this the error amplifier output is released to allow the soft start. The soft start time tSS represents the time during which converter voltage rises from zero to VO. tSS can be programmed by CSS using equation (4).
C SS
Once CSS is chosen, the soft start delay time tSSDEL, the over-current fault latch delay time tOCDEL, and the delay time tVccPG from output voltage (VO) in regulation to Power Good are fixed and shown in equation (5), (6) and (7) respectively.
Over Current Protection (OCP) The current limit threshold is set by a resistor connected between the OCSET and VDAC pins. If the average Current Sense Amplifier output plus VDAC voltage exceeds the OCSET voltage, the over-current protection is triggered. A delay is included if an over-current condition occurs after a successful soft-start sequence. This is required since overcurrent conditions can occur as part of normal operation due to load transients or VID transitions. If an over-current fault occurs during normal operation, the Over Current Comparator will initiate the discharge of the capacitor at SS/DEL but will not set the fault latch immediately. If the over-current condition persists long enough for the SS/DEL capacitor to discharge below the 250mV offset of the delay comparator, the Fault latch will be set pulling the Error Amplifier's output low inhibiting switching in the phase ICs and de-asserting the PWRGD signal. See Soft Start, Over-Current Fault Delay, and Hiccup Mode. The inductor DC resistance RL is utilized to sense the inductor current. ILIMIT is the required over current limit. IOCSET, the bias current of OCSET pin, is set by RROSC and is also determined by the curve in the Typical Operating Characteristics. ROCSET is defined in the following Equation (8).
ROCSET
(
I LIMIT Vo (Vin Vo) ) R L 23.5 / I OCSET 2 2 L Vin * fsw
Page 20 of 37
tVccPG
C SS * 'V I CHG
C SS * (3.75 VO 1.3) 55 * 10 6
t OCDEL
C SS * 'V I DISCHG
C SS * 0.25 50.5 * 10 6
t SSDEL
C SS * 'V I CHG
C SS * 1.3 55 * 10 6
I CHG * t SS VO
55 * 10 6 * t SS VO
(4)
(5)
(6)
(7)
(8)
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Adaptive Voltage Positioning Adaptive voltage positioning is needed to reduce output voltage deviations during load transients and power dissipation of the load when it is drawing maximum current. The circuitry related to voltage positioning is shown in Figure 9. Resistor RFB is connected between the Error Amplifier's inverting input pin FB and the converter's output voltage. An internal current source whose value is programmed by the same external resistor that programs the oscillator frequency, RROSC, pumps current out of the FB pin. The FB bias current develops a positioning voltage drop across RFB which forces the converter's output voltage lower to V(VDAC)-I(FB)* RFB to maintain a balance at the Error Amplifier inputs. RFB is selected to program the desired amount of fixed offset voltage below the DAC voltage. The voltage at the VDRP pin is an average of both phase Current Sense Amplifiers and represents the sum of the VDAC voltage and the average inductor current of all the phases. The VDRP pin is connected to the FB pin through the resistor. The Error Amplifier forces the voltage on the FB pin to equal VDAC through the power supply loop therefore the current through RDRP is equal to (VDRP-VDAC) / RDRP. As the load current increases, the VDRP voltage increases accordingly which results in an increase RFB current, further positioning the output regulated voltage lower thus making the output voltage reduction proportional to an increase in load current. The droop impedance or output impedance of the converter can thus be programmed by the resistor RDRP. The offset and slope of the converter output impedance are independent of the VDAC voltage. AMD specifies the acceptable power supply regulation window as 50mV around their specified VID tables. VR10.X specifies the VID table voltages as the absolute maximum power supply voltage. In order to have all three DAC options, the OPTERON and ATHLON DAC output voltages are pre-positioned 50mV higher than listed in AMD specs. During testing, a series resistor is placed between EAOUT and FB to cancel the additional 50mV out of the DAC. The FB bias current, equal to IROSC, develops the 50mV cancellation voltage. Trimming the VDAC voltage by monitoring V(EAOUT) with this 50mV cancellation resistor in circuit also trims out errors in the FB bias current. The VDRP pin voltage represents the average current of the converter plus the DAC voltage. The load current can be retrieved by subtracting the VDAC voltage from the VDRP voltage.
VDAC CDAC RDAC VOSNSVDAC ERROR AMPLIFIER
+
FB
RCOMP
IROSC
CCOMP
EAOUT
IROSC IDRP RDRP VDRP BUFFER VDRP
+
+
VPOSITIONING
VOUT SENSE+
RFB VOUT SENSE-
Figure 9 - Adaptive voltage positioning
Page 21 of 37
-
- V(CSavg) +
-
VDAC X24.5 CSINM3 CSINP3
+
VDAC X24.5 CSINM2
+
CSINP2
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A resistor RFB between FB pin and the converter output is used to create output voltage offset VO_NLOFST which is the difference between VDAC voltage and output voltage at no load condition. An internal current source whose value is programmed by the same external resistor that programs the oscillator frequency, RROSC, pumps current IROSC out of the FB pin. The voltage at the VDRP pin is an average of both phase Current Sense Amplifiers and represents the sum of the VDAC voltage and the average inductor current of all the phases. The VDRP pin is connected to the FB pin through the Adaptive Voltage Positioning Resistor RDRP. Adaptive voltage positioning lowers the converter voltage by RO*IO, where RO is the required output impedance of the converter. RFB and RDRP are determined by (9) and (10) respectively, where RO is the required output impedance of the converter.
R FB
R DRP
Lossless Average Inductor Current Sensing
VO _ NLOFST IROSC
R FB R L 23.5 2 RO
(9)
(10)
Inductor current can be sensed by connecting a series resistor and a capacitor network in parallel with the inductor and measuring the voltage across the capacitor. The equation of the sensing network is,
vC ( s )
v L ( s)
1 1 sRS C S
i L ( s)
R L sL 1 sRS C S
Usually the resistor Rcs and capacitor Ccs are chosen so that the time constant of Rcs and Ccs equals the time constant of the inductor which is the inductance L over the inductor DCR. If the two time constants match, the voltage across Ccs is proportional to the current through L, and the sense circuit can be treated as if only a sense resistor with the value of RL was used. The mismatch of the time constants does not affect the measurement of inductor DC current, but affects the AC component of the inductor current. The advantage of sensing the inductor current versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled information about the switch currents. The output voltage can be positioned to meet a load line based on real time information. Except for a sense resistor in series with the inductor, this is the only sense method that can support a single cycle transient response. Other methods provide no information during either load increase (low side sensing) or load decrease (high side sensing). An additional problem associated with peak or valley current mode control for voltage positioning is that they suffer from peak-to-average errors. These errors will show in many ways but one example is the effect of frequency variation. If the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and the output impedance of the converter will drop by about 10%. Variations in inductance, current sense amplifier bandwidth, PWM prop delay, any added slope compensation, input voltage, and output voltage are all additional sources of peak-to-average errors. The DC resistance of the inductor is utilized to sense the inductor current. Usually the resistor RCS and capacitor CCS in parallel with the inductor are chosen to match the time constant of the inductor, and therefore the voltage across the capacitor CCS represents the inductor current. If the two time constants are not the same, the AC component of the capacitor voltage is different from that of the real inductor current. The time constant mismatch does not affect the average current sharing among the multiple phases, but affects the AC component of the inductor current as well as the output voltage during the load current transient if adaptive voltage positioning is adopted.
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Measure the inductance L and the inductor DC resistance RL. Pre-select the capacitor CCS and calculate RCS as follows.
RCS
L RL CCS
(11)
The bias current flowing out of the non-inverting input of the current sense amplifier creates a voltage drop across RCS, which is equivalent to an input offset voltage of the current sense amplifier. The offset affects the accuracy of converter current signal ISHARE as well as the accuracy of the converter output voltage if adaptive voltage positioning is adopted. To reduce the offset voltage, a resistor RCSO should be added between the amplifier inverting input and the converter output, as shown in Fig1. The resistor RCSO is determined by the ratio of the bias current from the non-inverting input and the bias current from the inverting input.
|
RCSO
I CSIN RCS I CSIN
(12)
If RCSO is not used, RCS should be chosen so that the offset voltage is small enough. Usually RCS should be less than 2 k DQG WKHUHIRUH D ODUJHU &CS value is needed. Inductor DCR Temperature Correction If the Current Sense Amplifier temperature dependent gain is not adequate to compensate the inductor DCR TC, a negative temperature coefficient (NTC) thermistor can be added. The thermistor should be placed close to the inductor and connected in parallel with the feedback resistor, as shown in Figure 10. The resistor in series with the thermistor is used to reduce the nonlinearity of the thermistor.
VDAC
VDAC VOSNS-
ERROR AMPLIFIER
+
EAOUT
FB
IROSC VDRP BUFFER
+
RDRP
VDRP
VOUT SENSE+ RFB
RLINEAR
RNTC
Figure 10- Temperature compensation of inductor DCR Remote Voltage Sensing To compensate for impedance in the ground plane, the VOSNS- pin is used for remote sensing and connects directly to the load. The VDAC voltage is referenced to VOSNS- to avoid additional error terms or delay related to a separate differential amplifier. The capacitor connecting the VDAC and VOSNS- pins ensure that high speed transients are fed directly into the Error Amplifier without delay. Master-Slave Current Share Loop Current sharing between phases of the converter is achieved by a Master-Slave current share loop topology. The output of the Phase 1 Current Sense Amplifier sets the reference for the Share Adjust Error Amplifier. The Share Adjust Error Amplifier will then adjust the duty cycle of PWM Ramp2 to force its input error to zero, resulting in accurate current sharing. Page 23 of 37 06/25/04
-
-
Current + VDAC
IR3092
The maximum and minimum duty cycle adjust range of Ramp2 compared to Ramp1 has been limited to 0.5x and 2.0x of the master's ramp (see Figure 3.). The crossover frequency of the current share loop can be programmed with a capacitor at the SCOMP pin so that the share loop does not interact with the output voltage loop. A 22nF capacitor from SCOMP to LGND is good for most of the applications. If necessary have a 1k resistor in series with the Csc to make the current loop a little bit faster. The SCOMP capacitor is driven by a trans-conductance stage capable of sourcing and sinking 25uA. The duty cycle of Ramp2 inversely tracks the voltage on the SCOMP pin; if V(SCOMP) increases, Ramp2's slope will increase and the effective duty cycle will decrease resulting in a reduction in Phase 2's output current. Due to the limited 25uA source current, an SCOMP pre-charge circuit has been included to pre-condition V(SCOMP) so that the duty cycle of Ramp2 is equal to Ramp1 prior to any GATEHX high pulses. The pre-condition circuit can source 400uA. The Equal Duty Cycle Comparator (see Block Diagram) activates a pre-charge circuit when SS/DEL is less than 0.7V. The Error Amplifier becomes active enabling GATEH switching when SS/DEL is above 1.3V. Compensation of Voltage Loop The adaptive voltage positioning is used in the computer applications to meet the load line requirements. Like current mode control, the adaptive voltage positioning loop introduces extra zero to the voltage loop and splits the double poles of the power stage, which make the voltage loop compensation much easier. Resistors RFB and RDRP are chosen according to Equations (9) and (10), and the selection of compensation types depends on the capacitors used. For the applications using Electrolytic, Polymer or AL-Polymer capacitors, type II compensation shown in Figure 11 (a) is usually enough. While for the applications with only low ESR ceramic capacitors, type III compensation shown in Figure 11 (b) is preferred.
CCP1
CCP1
VO+
RFB
RCOMP
CCOMP
RCOMP
CCOMP
RFB1
CFB
FB
EAOUT EAOUT
VO+
RFB
FB
EAOUT EAOUT
VDRP
RDRP
VDAC
+
VDRP
RDRP
VDAC
+
CDRP
(a) Type II compensation
(b) Type III compensation
Figure11 . Voltage loop compensation network Type II Compensation Determine the compensation at no load, the worst case condition. Assume the time constant of the resistor and capacitor across the output inductors matches that of the inductor, the crossover frequency of the voltage loop can be estimated by Equations (13), where CE and RCE are the equivalent capacitance and ESR of output capacitors respectively and RLE is the equivalent resistance of inductor DCR.
fC
R DRP 2S * C E (GCS * R FB R LE RCE )
(13)
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RCOMP and CCOMP have limited effect on the crossover frequency, and are used only to fine tune the crossover frequency and transient load response. Choose the desired crossover frequency fc1 around fc estimated by Equation (13) and determine RCOMP and CCOMP.
RCOMP
C COMP
10 L E C E RCOMP
(2S f C1 ) 2 LE C E R FB V IN FM
(14)
(15)
CCP1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. A ceramic capacitor between 10pF and 220pF is usually enough. In equation (14), VIN is the input voltage, FM is the PWM comparator gain (refer to equation (22)). Type III Compensation Determine the compensation at no load, the worst case condition. Assume the time constant of the resistor and capacitor across the output inductors matches that of the inductor, the crossover frequency of the voltage loop can be estimated by Equations (16).
fC
R DRP 2S * C E GCS * R FB R LE
(16)
Choose the desired crossover frequency fc1 around fc estimated by Equation (16). Select other components to ensure the slope of close loop gain is -20dB/Dec around the crossover frequency. Choose resistor RFB1 according to Equation (17), and determine CFB and CDRP from Equations (18) and (19).
R FB1
1 R FB 2
to
R FB1
2 R FB 3
(17)
C FB
C DRP
4S f C1 R FB1
1
(18)
( R FB R FB1 ) C FB R DRP
(19)
RCOMP and CCOMP have limited effect on the crossover frequency, and are used only to fine tune the crossover frequency and transient load response. Determine RCOMP and CCOMP from Equations (20) and (21), where FM is the PWM comparator gain defined by Equation (22).
RCOMP
C COMP
(2S f C1 ) 2 LE C E R FB V I FM
10 LE C E RCOMP
(20)
(21)
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IR3092
FM VO V I * V RAMP
(22)
CCP1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. A ceramic capacitor between 10pF and 220pF is usually enough. Set BIASOUT Voltage Resistor Rset BIASOUT pin provides 150mA open-looped regulated voltage for GATE drive bias, and the voltage is set by SETBIAS through an external resistor Rset connecting between SETBIAS pin and ground. Bias current ISETBIAS is a function of ROSC. Rset is chosen by equation (23)
RSET
VBIASOUT ISETBIAS
(23)
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IR3092
DESIGN EXAMPLE IR3092 Demo Board Rev.2 for VRD10.0 FMB1.5 Specifications:
Input Voltage: VI=12 V DAC Voltage: VDAC=1.35 V No Load Output Voltage Offset: VO_NLOFST=25 mV Output Current: IO=80 A DC Output Current Limit set point: ILIMIT=100 A Output Impedance: RO=1.3 m VCC Ready to VCC Power Good Delay: tVccPG=0-10mS Soft Start Time: tSS=2 mS Dynamic VID Down-Slope Slew Rate: SRDOWN=2.5mV/uS
Power Stage Design
Control IC: IR3092 Phase Number: n=2 Switching Frequency: fSW=180 kHz Output Inductor(per phase): L=0.45 uH, RL=0.7 m (1m when winding temperatures around 120C) Output Capacitors: CE=0.011F, RCE=1 m
External Components of IR3092
Oscillator Resistor Rosc Once the switching frequency is chosen, ROSC can be determined from the curve in the datasheet of IR3092 data sheet. For switching frequency of 180 kHz per phase, Choose ROSC=47.5k Soft Start Capacitor CSS Calculate the soft start capacitor from the required soft start time 6mS.
With the selected Css value, we can calculate the following delay times: The Over-Current fault latch delay time tOCDEL will be:
Page 27 of 37
t OCDEL
C SS * 'V I DISCHG
0.1 * 10 6 * 0.25 50.5 * 10 6
0.5mS
C SS
I CHG * t SS VO
55 * 10 6 * 2 * 10 3 1.35 25 * 10 3
8.3 * 10 8 F
Choose CSS = 0.1 uF
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IR3092
The soft start delay time is
(c)
The power good delay time is
VDAC Slew Rate Programming Capacitor CDAC and Resistor RDAC From IR3092 data sheet, the sink current ISINK of VDAC pin corresponding to ROSC=47.5k LV X$ Calculate the VDAC down-slope slew-rate programming capacitor from the required down-slope slew rate.
Choose CVDAC=22nF Calculate the programming resistor.
In practice slightly adjust RDAC to get desired slew rate. The source current of VDAC pin is 55uA, and the VDAC up-slope slew rate is
Over Current Setting Resistor ROCSET According to the spec, the output current limit set point ILIMIT = 100A. The bias current IOCSET set by RROSC is around 26uA. Use Equation (10) to calculate the value of ROCSET:
= 52 k
&KRRVH 5OCSET=52.3K
No Load Output Voltage Setting Resistor RFB and Adaptive Voltage Positioning Resistor RDRP The value of the internal current source current IROSC (IFB in IR3092 datasheet curve) is 26uA according to RROSC = 47.5k
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ROCSET
(
(
I LIMIT Vo (Vin Vo ) ) R L 23 .5 / I OCSET 2 2 L Vin * fsw
SRUP
I SOURCE CVDAC
55 10 22 10
6 9
2.5mV / uS
R DAC
C DAC
2
0.5
3.2 10
15
0 .5
22 *10
3.2 * 10
15
CVDAC
I SINK SR DOWN
50 10 6 2.5 10 3 / 10
6
tVccPG
C SS * 'V I CHG
0.1 * 10 6 * (3.75 VO 1.3) 55 * 10 6
(c)
t SSDEL
C SS * 'V I CHG
0.1 * 10 6 * 1.3 55 * 10 6
2.3mS
2.0mS
20nF
92
7.1
100 1.325 * (12 1.325 ) 1 * 10 3 * 23 .5 )* 2 2 * 0.45 * 10 6 * 12 * 180 * 10 3 26 * 10 6
IR3092
R FB
IROSC
Inductor Current Sensing Capacitor CCS and Resistors RCS and RCSO Choose capacitor CCS = 0.22uF calculate RCS
The bias currents of CSIN+ and CSIN- are 0.2uA and 0.4uA respectively. Calculate resistor RCSO,
RCSO
I CSIN RCS I CSIN
0.2 * 3k: 1.5k: 0.4
Set BIASOUT voltage Resistor Rset Bias current ISETBIAS is around 95uA in this case. Set VBIASOUT around 8V to be gate drive voltage of MOSFETs.
Compensation of Voltage Loop AL-Polymer output capacitors are used in the design, and the crossover frequency of the voltage loop can be estimated as,
RCOMP and CCOMP are used to fine tune the crossover frequency and transient load response. Choose the desired crossover frequency fc1 (=25kHz) and determine RCOMP and CCOMP.
FM
RCOMP
VO V I V RAMP
(2S f C1 ) 2 LE C E RFB VI FM
1.325 12 0.63
0.175
(2S 25 103 ) 2 (450 10 9 / 2) 0.011 1 * 10 3 12 0.175
!
30k:
C COMP
10 LE C E RCOMP
10 (450 10 9 / 2) 0.011 30 10 3
17 nF
In practice, adjust RCOMP and CCOMP if need to get desired dynamic load response performance.
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fC
RDRP 2S CE (GCS RFB RLE RCE )
RSET
VBIASOUT ISETBIAS
8 95 * 10
6
84.21k:
RCS
L RL C CS
0.45 * 10 6 / 0.7 * 10 0.22 * 10 6
3
2.9k:
9.53 *103 17kHz 2S 0.011 [23.5 1*103 (0.7 *10 3 / 2) 1*10 3 ]
R DRP
R FB R L 23.5 2 RO
1 * 10 3 * 1 * 10 3 * 23.5 2 * 1.3 * 10 3
VO _ NLOFST
25 * 10 26 * 10
3 6
961
&KRRVH 5FB = 1k
9.4k:
Choose RDRP = 9.53k
Choose RCS=3k
Choose RSET=82.5k
IR3092
MathCAD file to estimate the power dissipation of the IC
Initial Conditions: IC Supply Voltage: Vcc 12 ( V) No.of Phases:
n 2
, IC Supply Current(quiescent): Icq
Iql 5 n
29 ( mA)
Total High side Driver VCCH supply current(quiescent): Total Low side Driver VCCL supply Current(quiescent):
fsw 200 ( kHz) Thermal Impedance of IC: T JA 27(oC/W) The data from the selected MOSFETs: Vbias
Iqh 5 n ( mA) ( mA)
Biasout Voltage:
7.5 ( V)
Switching Frequency per phase:
Control FET IR3715Z, Number of Control FET per phase: Control FET total gate charge: Sync FET total gate charge:
Qgc 11 ( nC)
nc 2 ns 2
Synchronous FET IR3717, Number of sync. FET per phase:
Qgs 33 (nC)
The IC will have less power dissipation if using external gate driver supply. For the worst case estimation, assume using the bias regulator for all the gate drive supply voltage. 1. Quiescent Power dissipation Total Quiescent Power Dissipation:
Pq ( Icq Iqh Iql) Vcc 10
"
3
Pq
0.588 ( W )
2. The Power Loss to drive the gate of the MOSFETs With the assumption of the low MOSFET gate resistances, most gate drive losses are dissipated in the driver circuit.
Pdrv Vbias fsw 10 n ( nc Qgc ns Qgs ) 10
3
#
9
Where the Ig fsw 10 n ( nc Qgc ns Qgs ) 10
3
1/4
Pdrv
0.264
(W)
9
term in the equation gives the total average
bias current required to drive all the MOSFETs. 3. The bias regulator Power Loss to supply driving the MOSFETs
Preg ( Vcc Vbias ) Ig Preg 0.158 (W)
4. Total Power Dissipation of the IC:
Pdiss Pq Pdrv Preg
Pdiss T JA
Pdiss 1.01 (W) oC) (
And the total Junction temperature rising is:
27.281
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IR3092
OVP ENABLE 12VIN
LGND SETBIAS VCC NC NC BIASOUT PWRGD CSINP2 NC VID_SEL NC NC
VID3 VID4 ROSC VOSNSOCSET VDAC VDRP FB EAOUT SS/DEL SCOMP NC
VID2 VID1 VID0 VID5 NC NC ENABLE OVP CSINP1 CSINM NC VCCH1
VID5 VID0 VID1 VID2 VID3 VID4
1
2
IR3092
48LD MLPQ
GATEH1 PGND1 GATEL1 VCCL 5VUVL GATEL2 PGND2 GATEH2 VCCH2 NC NC NC
12VIN
1
2
VCORE
VRETURN
12VIN POWERGOOD
Figure 12. 12V Control, 12V Power Opteron Converter
OVP ENABLE 12VIN
5VIN
1
LGND SETBIAS VCC NC NC BIASOUT PWRGD CSINP2 NC VID_SEL NC NC
VID3 VID4 ROSC VOSNSOCSET VDAC VDRP FB EAOUT SS/DEL SCOMP NC
VID2 VID1 VID0 VID5 NC NC ENABLE OVP CSINP1 CSINM NC VCCH1
VID5 VID0 VID1 VID2 VID3 VID4
1
2
IR3092
48LD MLPQ
GATEH1 PGND1 GATEL1 VCCL 5VUVL GATEL2 PGND2 GATEH2 VCCH2 NC NC NC
5VIN
1
2
VCORE
5VIN
VRETURN
12VIN POWERGOOD
Figure 13. 12V Control, 5V Power, VR10.0 Converter
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IR3092
LAYOUT GUIDELINES
The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB layout, therefore minimizing the noise coupled to the IC. Refer to the schematic in Figure 6 - System Diagram. x x x x x x x x x x x Dedicate at least one inner layer of the PCB as power ground plane (PGND). The center pad of IC must be connected to ground plane (PGND) using the recommended via pattern shown in "PCB and Stencil Design Methodology". The IC's PGND1, 2 and LGND should connect to the center pad under IC. The following components must be grounded directly to the LGND pin on the IC using a ground plane on the component side of PCB: CSS, RSC2, RSET, and CVCC. The LGND should only be connected to ground plane on the center pad under IC Place the decoupling capacitors CVCC and CBIAS as close as possible to the VCC and VCCL pins. The ground side of CBIAS should not be connected to LGND and it should directly be grounded through vias. The following components should be placed as close as possible to the respective pins on the IC: RROSC, ROCSET, CDAC, RDAC, CSS, CSC2, RSC2, CCOMP RCOMP and RSET. Place current sense capacitors CCS1, 2 and resistors RCS1, 2 as close as possible to CSINP1, 2 pins of IC and route the two current sense signals in pairs connecting to the IC. The current sense signals should be located away from gate drive signals and switch nodes. Use Kelvin connections to route the current sense traces to each individual phase inductor, in order to achieve good current share between phases. Place the input decoupling capacitors closer to the drain of top MOSFET and the source of the bottom MOSFET. If possible, use multiple smaller value ceramic caps instead of one big cap, or use low inductance type of ceramic cap, to reduce the parasitic inductance. Route the high current paths using wide and short traces or polygons. Use multiple vias for connections between layers. The symmetry of the following connections from phase to phase is important for proper operation: - The Kelvin connections of the current sense signals to inductors. - The gate drive signals from the IC to the MOSFETS. - The polygon shape of switching nodes.
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IR3092
PCB AND STENCIL DESIGN METHODOLOGY
x x x 7x7 48 Lead 0.5mm pitch MLPQ
See Figures 14-16. PCB Metal Design (0.5mm Pitch Leads) 1. Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should be PP WR PLQLPL]H VKRUWLQJ 2. Lead land length should be equal to maximum part lead length + 0.2 mm outboard extension + 0.05mm inboard extension. The outboard extension ensures a large and inspectable toe fillet, and the inboard extension will accommodate any part misalignment and ensure a fillet. 3. Center pad land length and width should be = maximum part pad length and width. However, the minimum metal to metal spacing should be PP R] &RSSHU PP IRU R] &RSSHU and PP IRU R] &RSSHU 4. Sixteen 0.30mm diameter vias shall be placed in the pad land spaced at 1.2mm, and connected to ground to minimize the noise effect on the IC, and to transfer heat to the PCB. PCB Solder Resist Design (0.5mm Pitch Leads) 1. Lead lands. The solder resist should be pulled away from the metal lead lands by a minimum of 0.060mm. The solder resist mis-alignment is a maximum of 0.050mm and it is recommended that the lead lands are all NSMD. Therefore pulling the S/R 0.060mm will always ensure NSMD pads. 2. The minimum solder resist width is 0.13mm, therefore it is recommended that the solder resist is completely removed from between the lead lands forming a single opening for each "group" of lead lands. 3. At the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a fillet so a solder resist width of PP UHPDLQV 4. Land Pad. The land pad should be SMD, with a minimum overlap of the solder resist onto the copper of 0.060mm to accommodate solder resist mis-alignment. In 0.5mm pitch cases it is allowable to have the solder resist opening for the land pad to be smaller than the part pad. 5. Ensure that the solder resist in-between the lead lands and the pad land is PP GXH WR WKH high aspect ratio of the solder resist strip separating the lead lands from the pad land. 6. The single via in the land pad should be tented with solder resist 0.4mm diameter, or 0.1mm larger than the diameter of the via. Stencil Design (0.5mm Pitch Leads) 1. The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release. 2. The stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead land. 3. The center land pad aperture should be striped with 0.25mm wide openings and spaces to deposit approximately 50% area of solder on the center pad. If too much solder is deposited on the center land pad the part will float and the lead lands will be open. 4. The maximum length and width of the center land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste.
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IR3092
Figure 14. PCB metal and solder resist.
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IR3092
Figure 15. PCB metal and component placement.
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IR3092
Figure 16. Stencil design.
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IR3092
PACKAGE DIMENSIONS
Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information
www.irf.com
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06/25/04

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